This invention relates to programmable logic integrated circuit devices, and more particularly to function-specific blocks such as multipliers, arithmetic logic units, barrel shifters, and/or the like in programmable logic devices.
Programmable logic devices (xe2x80x9cPLDsxe2x80x9d) are well known as is shown, for example, by Jefferson et al. U.S. Pat. No. 6,215,326 and Ngai et al. U.S. Pat. No. 6,407,576. PLDs typically include many regions of programmable logic that are interconnectable in any of many different ways by programmable interconnection resources. Each logic region is programmable to perform any of several logic functions on input signals applied to that region from the interconnection resources. As a result of the logic function(s) it performs, each logic region produces one or more output signals that are applied to the interconnection resources. The interconnection resources typically include drivers, interconnection conductors, and programmable switches for selectively making connections between various interconnection conductors. The interconnection resources can generally be used to connect any logic region output to any logic region input; although to avoid having to devote a disproportionately large fraction of the device to interconnection resources, it is usually the case that only a subset of all possible interconnections can be made in any given programmed configuration of the PLD. Indeed, this last point is very important in the design of PLDs because interconnection resources must always be somewhat limited in PLDs having large logic capacity, and interconnection arrangements must therefore be provided that are flexible, efficient, and of adequate capacity without displacing excessive amounts of other resources such as logic.
Although only logic regions are mentioned above, it should also be noted that many PLDs also now include regions of memory that can be used as random access memory (xe2x80x9cRAMxe2x80x9d), read-only memory (xe2x80x9cROMxe2x80x9d), content addressable memory (xe2x80x9cCAMxe2x80x9d), product term (xe2x80x9cp-termxe2x80x9d) logic, etc.
As the capacity and speed of PLDs has increased, there has been increasing interest in using them for signal or data processing tasks that may involve relatively large amounts of parallel information and that may require relatively complex manipulation, combination, and recombination of that information. Large numbers of signals in parallel consume a correspondingly large amount of interconnection resources; and each time that information (or another combination or recombination that includes that information) must be routed within the device, another similar large amount of the interconnection resources is consumed. Improved PLD architectures are needed to better address these issues.
A PLD in accordance with this invention includes a plurality of regions of programmable logic circuitry, general purpose interconnection circuitry that is programmably configurable to allow outputs of substantially any of the regions to be applied to inputs of substantially any of the regions, function-specific circuitry, and routing circuitry that is programmably configurable to route outputs of the function-specific circuitry to only a subset of the regions.
A function-specific block (xe2x80x9cFSBxe2x80x9d) typically has a plurality of parallel inputs and a plurality of parallel outputs. An FSB is at least partly hard-wired to perform a particular task or tasks on its inputs to produce its outputs. The task(s) performed by an FSB may be wholly or partly, programmably or dynamically, selectable. Examples of FSBs include parallel multipliers, parallel arithmetic logic units (xe2x80x9cALUsxe2x80x9d), barrel shifters, and the like.
In order to reduce the impact of including FSBs on the interconnection resources of the PLD, any or all of several techniques respecting the interconnection resources may be used in accordance with this invention. One technique is to derive inputs for the FSB from interconnection resources that are already fairly local (i.e., close) to the inputs of other resources such as logic regions (or memory regions if memory regions are included (although borrowing inputs from logic is presently preferred)). In this way the FSB effectively shares substantial amounts of input routing resources with those other (logic/memory/etc.) resources. A smaller fraction of the overall interconnection resources must be dedicated to providing FSB inputs, and the impact on use of the more global (as opposed to the local) interconnection resources is especially reduced. (Global interconnection resources include relatively long interconnection conductors, in contrast to the relatively short conductors that can be used for more local interconnections. Accordingly, it is xe2x80x9cmore expensivexe2x80x9d to use a global interconnection conductor than a local interconnection conductor. Also, global interconnection conductors tend to be slow and to require drive by power-consuming drivers, whereas local conductors tend to be faster and may not require additional drivers.) Sharing an interconnection resource between an FSB input and another logic/memory/etc. resource input may reduce or even sacrifice the usability of the other resource when the PLD is configured to use the FSB, but that can be preferable to having to provide more interconnection resources that are dedicated to providing FSB inputs.
Another technique that can be-used to reduce the impact of an FSB on the interconnection resources of a PLD is to use relatively local interconnection resources for the outputs of the FSB. These local resources can be used to supply the FSB outputs to the inputs (or other relatively local interconnection resources leading to the inputs) of particular subsets of other resources such as logic regions on the PLD. This avoids the need for drivers and/or more global interconnection conductors dedicated to the FSB outputs. If FSB output driving by drivers is needed, the output drivers of the immediately above-mentioned logic regions can be used. Similarly, if the FSB outputs need registering, the registers of these logic regions can be used. And these logic regions can even be used to at least begin further logical and/or arithmetic manipulation of the FSB outputs. Once again, this effective sharing of certain FSB output functions with logic regions may reduce or sacrifice the usefulness of those logic regions for other purposes when the FSB is being used, but that can be preferable to having to provide more dedicated interconnection resources to support the FSB.
Other aspects of the invention may be used to facilitate providing arithmetic accumulation of successive FSB (especially multiplier) outputs (using either addition or subtraction), addition or other logical combination of multiple concurrent FSB (especially multiplier) outputs, sign extension of FSB (especially multiplier) outputs, registration of FSB inputs and/or outputs, etc.